V5.2 Overview | V5.2 Features | V5.2 Deliverables | V5.2 FAQ

V5.2 Features

Following are some of the key features of Aricent V5 Signaling product:

• All Aricent signaling products use a common Protocol Framework AAPE™, thus giving them all a similar look and feel. The V5 product also follows this framework and thus special consideration has been given to CPU and memory efficiency.
  
  
• The V5 product has a Distributed Architecture and has been ported onto a wide range of operating environments - from hybrid-multiprocessor environments to a single processor flat memory type of environments.
  
  
• The V5 product provides multiple options for Redundancy Support.
  
  
• Customizable Error Handling allows handling an error in the context in which it occurs.
  
  
• Flexible memory allocation of all internal data structures (either dynamic or static) is used to achieve minimum memory utilization for the customer system’s configuration.
  
  
• Simple and easy to port OS interfaces are provided. The product has already been ported to Solaris, VxWorks, pSOS, Windows NT and other proprietary OS environments.
  
  
• Accurate statistics and debug traces support is provided.
  
  
• Interfaces to the stack (APIs) are user friendly and intuitive.
  
  
• A host of compile time options are provided to configure the product as per the customer’s system.
  
  
• TMN Compliant Q3 interfaces are also provided.
  
  
• The documentation provided is elaborate and accurate.
  

Conformance to Standards

The Aricent V5 Signaling stack product conforms to the following standards:

• ETS 300 324-1, ETS 300 324-2 : V5.1 Interface Specifications
• ETS 300 324-1, ETS 300 324-2 : A1 January 1996 Amendment to V5.1 interface specification
• ETS 300 347-1, ETS 300 347-2 : V5.2 Interface Specifications
• ETS 300 347-1, ETS 300 347-2 : A1 May 1997 Amendment to V5.2 Interface Specification

Last updated : March 20, 2006